— Silicon

Radiation-hardened microchips. Designed from scratch.

We design the silicon that goes inside our boards — and inside other people's. Configurable digital and analogue blocks, tight DA integration, and a cloud-based design and verification stack. Three months from architecture freeze to tapeout. Six times faster than the status quo.

Process22 FDX · 28 nm bulk

SEUTriplicated registers

SELLatch-up immune to 80 MeV·cm²/mg

TID≥ 300 krad(Si)

— 01 / The chips

Three IP families. Configurable, qualifiable, integrable.

— 01.1 SPH-D

Digital.

RISC-V core with hardened cache, FDIR, and bus arbitration. Triplicated state, scrubbed on idle.

22 FDX · 600 MHz

— 01.2 SPH-A

Analogue.

LDOs, ADCs, DACs and references. Configurable bias trees; calibrated post-irradiation in firmware.

28 nm bulk · 0.8–3.6 V

— 01.3 SPH-RF

Mixed-signal.

S-band and X-band transceiver tiles. Direct-conversion, on-die filtering, programmable PA driver.

2.0–8.4 GHz · 2 W TX

— 02 / Method

A modern, cloud-native design stack. Automated where it matters; reviewed where it counts.

Cloud-native EDA

Synthesis, P&R, and DRC orchestrated in containers. We rebuild the chip overnight; you see the report at 0700.

ii.

Machine-learning assisted layout

Constraint-driven placement closes timing on the first pass for ~80% of blocks. The remaining 20% is where engineers earn their keep.

iii.

Configurable building blocks

Hardened cells, qualified once, reused across programmes. Each block ships with its own characterisation report and irradiation history.

iv.

Tight digital–analogue integration

DA on the same die, with hooks designed in for software-defined behaviour. The system architect and the layout engineer share a Slack channel.

Fig. 01SPH-D floorplan, 12 mm² at 22 FDX.

Fig. 02Block-level configurable architecture.

Fig. 03SPH-RF transceiver tile, X-band variant.

— 03 / Engagement

Three ways to work with us on silicon.

Mode	What you get	Lead time	NRE
CatalogueStock SPH parts	Hardened blocks, datasheet, eval kit	8 weeks	—
ConfiguredSPH IP, your spec	Re-parameterised block, MPW tapeout	4 months	€ low
CustomNew ASIC, full programme	Architecture → tapeout → qualification	9–12 months	€ programme

— Silicon enquiry

Talk to a chip architect, not an account manager.

Silicon enquiry Systems →